Good practice in DfT during SoC design and verification can improve time to market and reduce manufacturing costs. For the automotive sector being conversant with its rigorous IC design requirements is critical. In order to optimise a test strategy, you have to take into account the functional safety standard ISO 26262 using ASIL levels (Automotive Safety Integrity Level) specific coverage targets.
As more and more functions are integrated on automotive ICs it is becoming increasingly challenging to adequately test these devices in production and ensure self-test during their life cycle. Traditional scan techniques alone are just too slow and do not take into account automotive safety requirements. They lack capacity and do not offer the capability of self-test of the device during the real application. As a result, new DfT techniques have been introduced to address the challenges. These techniques increase the testability of the design and reduce production test times, but require additional design effort across multiple disciplines.
To meet the quality and reliability requirements of the ISO 26262 and other automotive electronics standards “infield” chip testing is necessary. Logicbist provides an infield and system testing method throughout the product life cycle and can also be used for fast manufacturing test bring up, thereby reducing expensive test time.
Internal JTAG P1687 can be applied. IJTAG replaces ad-hoc communication methods for controlling on-chip test structures and embedded instruments enabling higher degrees of interoperability and DfT re-use. This allows easier integration of on-chip embedded instruments such as PLL, BIST and memory BIST with sophisticated memory test pattern generation and repair.
Today’s EDA tools enable a large degree of automation in the DfT flow. However it is still necessary that DfT guidelines are applied during RTL design to ensure that the design is highly testable. This will ensure the best test QoR (highest coverage/lowest test time).
DfT for complex SoC designs cannot be considered in isolation. Physical design has a significant impact on the DfT implementation, and expertise in physical design pays dividends for DfT ensuring:
- Optimal partitioning of test compression.
- Architecture of memory BIST controllers
- STA of test modes to ensure that DfT minimises impact on functional timing closure.
Once the test features have been implemented you can generate and verify the test patterns that will help with the transfer of the patterns to the test house of your choice.
If any issues are identified during post-silicon validation, with diagnostic tools you can identify design issues and enhance the test vectors to accommodate any changes that may be required.