Sondrel Ltd

Formal Verification Design Consultancy Datasheet

Document   •   Jan 07, 2016 08:26 GMT

Formal verification is an umbrella term for techniques that use static analysis based on mathematical transformations to determine if hardware or software will behave correctly. This is in contrast to dynamic verification techniques such as simulation that sequentially apply stimuli to a design under test (DUT) and to check the corresponding responses.
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