Modern SoCs are required to make efficient use of the power source to extend battery life or minimize energy requirements. Sophisticated power management strategies such as clock gating, multiple clock and power domains, or dynamic voltage and frequency scaling (DVFS) result in complex on-chip power networks. This adds significant complexity and effort to design verification, which must ensure the device operates correctly in numerous possible power states.
Sondrel’s expertise includes development of the verification plan including suitable coverage of power intent, testbench development, power aware simulation and debug of the most advanced power networks captured in UPF or CPF formats.
You can learn more about the benefits of this consultancy service in the Power Integrity Verification Consultancy Datasheet.
Contact Sondrel today to discuss your IC project and ensure you have the right verification strategy in place for your design.
Success through Partnership is the philosophy of Sondrel, one of the world’s leading system-to-silicon IC consultancies. For Sondrel, Partnership means sharing the responsibility to get a project done for the mutual benefit of all parties – customer, design house, foundries and tools & IP providers. Established in 2002, Sondrel has the largest and most experienced consulting team in Europe, with wide ranging expertise across all aspects of the design flow and all industry-standard EDA tool suits. The company’s capabilities cover the entire IC design spectrum from RTL design, though verification, emulation and DFT to physical implementation, and include power analysis and yield management. Sondrel is experienced in highly-complex digital, mixed signal, analogue, low power and wireless designs having completed over 250 designs at a range of process geometries down to 14nm, all of which were delivered right first time. With offices in the EMEA, USA and Asia, Sondrel provides flexible services and methodology consulting to many of the world’s leading semiconductor companies, enabling them to improve chip performance and reduce timescales and costs.